Delay locked loops (DLL) are commonly used for generating timing reference signals used in electronic circuits. A typical delay locked loop is configured as shown in FIGS. 1A-1C, and functions generally as follows.
Now referring to FIGS. 1A-1C, an input signal denoted as CLK IN is placed on input line 20 of delay lock loop 22. The CLK IN signal is also applied to line 24 which is the input to delay element 26. Phase detector 28 functions to compare the phase difference between the signals present on lines 20 and 30 and generate an output on lines 32 and 34 representative of the phase difference between the signals present on lines 20 and 30. For example, if the signal present on line 20 leads the signal on line 30, a signal is present on line 32 commanding charge pump 38 to drive the voltage on line 36 higher. Likewise, if the signal on line 30 leads the signal on line 20, a signal is present on line 34 to command charge pump 38 to lower the voltage present on output line 36. The output voltage 36 is passed to low pass filter 40 where it is filtered and delivered to delay element 26 along line 42. Delay element 26 functions to delay the signal present on line 24 in proportion to the voltage present on line 42. This delayed signal is placed on output line 44 and is fed back along line 30 into phase detector 28.
FIG. 1B shows a hypothetical signal which is placed on line 20 (and also placed into delay element 26 by virtue of line 24). After a certain transient period, delay element 26 will be responsible for time delaying the signal on line 24 by the time increment t.sub.1. This time delayed signal (see FIG. 1C) is placed on line 44 where it is fed back to phase detector 28 along line 30. Because signals represented in FIGS. 1B and 1C are in phase, the output of phase detector 28 is null and charge pump 38 neither increases or decreases its voltage on output line 36. Thus, delay element 26, under these conditions, maintains whatever delay it is introducing (t.sub.1) and the delay lock loop is successful in locking the output signal (CLK OUT) in phase with the input signal (CLK IN).
If during the operation of the delay lock loop of FIG. 1A, there develops a phase difference between CLK IN signal and CLK OUT signal, this will result in a phase error detected by phase detector 28 which results in a command to charge pump 38 to generate a voltage on line 36 which tends to drive delay element 26 in a direction which causes a phase delay in the signal present on output line 44 to lessen the phase difference between the signal present on CLK IN and the CLK OUT signal. Thus, it has been demonstrated that the delay lock loop of FIG. 1A tends to correct any phase error which exists between the CLK IN signal and the CLK OUT signal.
Although the operation of the typical prior art delay lock loop can generally be described as has been set forth above, there are certain drawbacks with delay lock loops when they are designed without upper and lower control limits on the amount of delay entered by delay element 26. Two articles published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS address this problem and set forth solutions for controlling the absolute limits of the delay element (see IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 12, DEC. 1992 and VOL. 23, NO. 5, October 1988). Although, such attempts to limit the control limits of the delay line may be successful, they are specific to their particular implementation of the delay element and none of them are generic or easily expandable to alternative implementations of delay elements.
It is well understood that if upper and lower limits are not placed on the time delay introduced by the delay element 26, two types of erroneous modes of operation can occur--harmonic lock or ambiguity in detecting the correct phase error (hereinafter phase ambiguity). These two erroneous modes of operation will now be explained.
Now referring to FIGS. 1A, 2A and 2B, harmonic lock occurs when the delay element 26 is introducing a large delay into the CLK OUT signal but the resultant delay is such that the output signal generated by delay element 26 has a period which is an integer multiple of the period of the CLK IN signal. Under these conditions, phase detector 28 of delay lock loop 22 will not detect a phase error between the signals present on lines 20 and 30 and therefore it cannot differentiate the correct running of the delay locked loop from the incorrect operation of the delay lock loop. For example (see FIGS. 2A and 2B) if the incoming signal has a period of 40 ns and the delay element starts up at an 80 ns delay increment, the phase detector will observe one rising clock edge 52 exiting delay element 26 every 40 ns which satisfies the criteria for a locked condition. Thus, in this case, the delay lock loop will be "fooled" into locking into an 80 ns pulse delay when in fact it should be locking into a 40 ns pulse delay.
The second error condition, phase ambiguity, will be explained in conjunction with FIGS. 1A, and 3A-3C. It is critical to the correct operation of the phase detector 28 that it be capable of determining whether the phase error is positive or negative (i.e. whether the CLK IN signal leads or lags the CLK OUT signal). If the phase detector enters into a mode whereby it cannot correctly decipher between the two conditions, the phase detector will generate erroneous phase information. Thus, as is illustrated in FIGS. 3A and 3B, the phase difference between the CLK OUT signal and the CLK IN signal is either the phase delay indicated at 54 or the phase advance indicated at 56 depending upon which rising edge 57, 59 is used as the reference point. Likewise, in comparing the signal of FIG. 3B with the signal of FIG. 3C the resulting phase delay between the two signals can either be the phase advance indicated at 58 or the phase delay indicated at 60 depending upon which rising edge 57, 59 is used as the reference point.
The present invention sets forth a system for eliminating harmonic lock and phase ambiguity.
Thus it is an object of this invention to provide a delayed-lock loop which controls the absolute limit of its delay element in a way which allows the delay lock loop to offer superior operation to that of the known prior art delay lock loops and also in a way which is not limited to particular implementations of delay elements but are generic and easily expandable to any type of delay element.
Also, it is an object of this invention to provide a circuit for controlling the upper limit of the delay line such that the delay lock loop cannot enter into a harmonic lock condition when it is running at an integer multiple of the reference signal.